Kyoto (Japan) – Intel has unveiled research results of new I/O technology that improves the power efficiency of existing architectures such as PCI Express by a factor of 7.
As we are heading deeper into the multi-core space, hardware manufacturers are likely to be facing a capacity and power bottleneck at the I/O transceiver. Processors with potentially dozens of cores are calling for significantly faster and more power efficient on-chip and off-chip interfaces to take advantage of the additional processing power.
Intel said that it has developed a new technology, which only consumes about 14% of the power of PCI Express 2.0. At a maximum data rate of 5 Gb/s, PCI Express 2.0 consumes about 20 mWatts per Gb/s bandwidth. Intel claims that its new and not yet named technology can achieve 5 Gb/s at about 2.7 mWatts per Gb/s.
So far, the power efficiency of the technology is scaling almost linearly and achieved 3.6 mWatts per GB/s at 10 Gb/s and 5.0 mWatts per Gb/s at 15 Gb/s – which, to our knowledge, is the best power efficiency result for I/O receivers achieved so far. Infineon claimed the crown in this category in February 2006, when it disclosed details about a 9.6 Gb/s transceiver running at 10.4 mWatts per Gb/s.
At least in theory, Intel’s interface could bump the available bandwidth of today’s available bandwidth by a factor of 3 while consuming 75% less power. Randy Mooney, a Fellow and director of I/O research at Intel, however, pointed out that the technology is still at a research stage.
He confirmed that we could see the technology surfacing within a few years in Intel products, but declined to comment on specific products. Instead, Rooney explained that the new I/O findings will be a key technology in enabling “a large number” of cores (which means more than 10 cores, according to company representatives). Example applications could include point-to-point links in microprocessors, which will replace the front side bus in today’s Intel architecture.