Austin (TX) - Convey Computer Corporation announced today the world's first hybrid core computer. Their design utilizes Intel Xeon processors and custom engineered Xilinx FPGA co-processors which, like the old 80387 FPU chips, process data alongside their x86 counterpart. Sharing the same real and virtualy memory space, this design also allows for significant advances in performance per watt. Convey uses ANSI standard C/C++/Fortran, making development much simpler and almost entirely x86-based.
Special-purpose computing
According to Dr. Larry Smarr, director of the California Institute for Telecommunications and Information Technology, "The HC-1 is a remarkably ingenuous and innovative HPC architecture, which combines the best of both worlds of special purpose multi-core and special-purpose FPGAs." Smarr calls the HC-1 a "new class" of HPC architecture.
The custom-developed co-processor appears to developers as a mere extension of the traditional x86 ISA. They share the same physical and virtual address spaces, and each application can contain both x86 and co-processor instructions embedded within a single application and single instruction stream, as is generated by the Convey compilers.
Pat Gelsinger, Intel's senior VP and GM of its Digital Enterprise Group, said, "Convey’s system is unique in that it does not require programmers to instrument their code but, instead, provides an open-standard programming model that does not use proprietary mechanisms that have historically limited adoption of heterogeneous solutions."
She's got ... personalities!
While targeted for a wide array of compute-intensive applications, such as financial, seismic and biomedical, the compiler design integrates something called "personalities." A personality allows the targeted application to render the FPGA in specific ways to enhance throughput for that application model and workload.
This ability also creates a framework which, while maintaining full binary compatibility across the board, allows certain operations in one configuration to utilize more of the custom core, thereby allowing it to process data faster.
Bandwidths of up to 80 GB/s and a cache-coherency system allow everything to be kept in sequence. In fact, from all outward appearances to the developer, this is a single x86-based machine with add-on extensions in the form of a customizable co-processor. This is similar to the way the old 8087/80287/80387 FPU co-processors used to plug in to the early motherboards.
The design was announced today at the Supercomputing Conference 2008 in Austin, Texas. It runs the Linux operating system in a 2U chassis.
Special-purpose computing
According to Dr. Larry Smarr, director of the California Institute for Telecommunications and Information Technology, "The HC-1 is a remarkably ingenuous and innovative HPC architecture, which combines the best of both worlds of special purpose multi-core and special-purpose FPGAs." Smarr calls the HC-1 a "new class" of HPC architecture.
The custom-developed co-processor appears to developers as a mere extension of the traditional x86 ISA. They share the same physical and virtual address spaces, and each application can contain both x86 and co-processor instructions embedded within a single application and single instruction stream, as is generated by the Convey compilers.
Pat Gelsinger, Intel's senior VP and GM of its Digital Enterprise Group, said, "Convey’s system is unique in that it does not require programmers to instrument their code but, instead, provides an open-standard programming model that does not use proprietary mechanisms that have historically limited adoption of heterogeneous solutions."
She's got ... personalities!
While targeted for a wide array of compute-intensive applications, such as financial, seismic and biomedical, the compiler design integrates something called "personalities." A personality allows the targeted application to render the FPGA in specific ways to enhance throughput for that application model and workload.
This ability also creates a framework which, while maintaining full binary compatibility across the board, allows certain operations in one configuration to utilize more of the custom core, thereby allowing it to process data faster.
Bandwidths of up to 80 GB/s and a cache-coherency system allow everything to be kept in sequence. In fact, from all outward appearances to the developer, this is a single x86-based machine with add-on extensions in the form of a customizable co-processor. This is similar to the way the old 8087/80287/80387 FPU co-processors used to plug in to the early motherboards.
The design was announced today at the Supercomputing Conference 2008 in Austin, Texas. It runs the Linux operating system in a 2U chassis.
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