IBM drives 3D processor stacking technology closer to production
Armonk (NY) – Stacking silicon to increase densities isn’t an entirely new concept – Flash and DRAM memory manufacturers have been using the approach for some time now. However, while the idea has been discussed for microprocessors as well, no clear products have been unveiled so far: IBM today said that it wants to put 3D processors into mass production in 2008.
IBM’s announcement follows the same approach of what we have seen for example in Infineon’s high-capacity server memory or in newer generation stacked flash memory devices: Stacked silicon, rather than placed side-by-side, saves space, shortens data travel distances, and ultimately saves a whole lot of space and offers an opportunity to extend Moore’s Law, which has become a key focus for the hardware industry.
To connect the individual pieces of a chip sandwich, IBM uses a technology called “through-silicon vias” (derived from the Latin word via = way, road), which are vertical connections etched through the silicon wafer and filled with metal. This concept has been described by other chip manufacturers before, perhaps most noteworthy by Intel, which laid out a 3D stacking concept for microprocessors at its Spring IDF in 2005.
“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the “lab to the fab” across a range of applications.” IBM believes that it can use the technology for both processor-on-processor and memory-on-processor chip designs. The company confirmed that it is “fabricating” stacked 3D SRAM chips on 300 mm wafers at this time and that it is working on a 3D stacked version of its PowerPC 440 processor, which is used in the BlueGene/L supercomputer.
First 3D sample chips are expected to be available to customers in the second half of 2007, with production scheduled to be running in 2008.