Chicago (IL) - Today, NEC announced the successful operation of a 32 Mb MRAM (Magnetic Random Access Memory) that can be embedded in SoCs. Each bit contains only one transistor and one MTJ (magnetic tunneling junction) per cell and achieves a 73% efficient use of surface area and a 9 ns cycle time. The MRAM cell was also made compatible with asynchronous SRAM by utilizing protocol transform circuits between MRAM macro and SRAM I/O. Additional modified protocol transforms are possible making MRAM compatible with any existing form of RAM or Flash.







Here we see a 32 Mb array (4 Megabytes). In November 2007, NEC demonstrated a 250 MHz 1 Mb MRAM with two transistors and one MTJ per cell. The new solution has only one transistor and one MTJ per cell. As with early implementations of DRAM, several chips like this can be placed onto a single board, allowing for larger memory modules of 32 Megabytes, 64 Megabytes, and so on.


MRAM is desirable because, like Flash, it is a non-volatile storage medium, and yet its speed is comparable to that of the fastest memory available today, which is the SRAM used in CPU caches. Such memory technology has been a form of holy grail long sought after in this industry for two other reasons as well. First, it would allow for always-on or instant-on computers that do not require power to maintain the memory state once data is written (because it is non-volatile). Second, a CPU could be put into a C6 or higher sleep state, with no power required for memory circuitry at all, and only fractional milliwatts required for the CPU, allowing for stand-by battery life lasting for a year or more. And, once re-activated, the computer would not require load time. It would simply be immediately available again.

Such technology would greatly improve notebook battery life even today as MRAM could serve not only as a replacement for RAM, but also for hard drives and SSDs. In addition, since the memory does not have to be constantly refreshed, the faster the CPU could enter its C6 or higher sleep state, the longer the computer would last. Introduce OLED or switching LCD displays (which maintain their state when the power is off), and some really exciting long-life devices become possible.



NEC had to overcome engineering challenges to allow generic operation in a system board. First, the internal requirements of working within the 32 Mb MRAM chip mandated a reworking of NEC's "word boost circuits." This was accomplished by introducing "optimized conversion levels" which allowed for the 9 ns response over the entire 32 Mb (4 Megabyte) array. Once that was achieved the need for a generic ability to convert the internal data format to that of modern memory systems had to be created.



NEC developed protocol transfer circuits which operate as go-betweens. One side talks to the conventional memory format, the other to the internal storage mechanisms in the MRAM array. Since this circuit has two sides, each can be adapted independently of the other, allowing for custom protocol transform circuits which operate with any form of conventional memory.



According to the press release, "The successful operating demonstration of the 32Mb MRAM indicates that MRAM macros using high speed MRAM cells are, in fact, able to enlarge their capacity. It also widens the field of application for system LSIs where memory macros are substituted for MRAMs. Looking forward, NEC is aiming to demonstrate an SoC integrated with large capacity, high speed MRAM macros."



Funding was provided for this research by NEC Corporation, NEC Electronics Corporation, and is partially supported by the New Energy and Industrial Technology Development Organization's (NEDO) MRAM technology development project for the realization of high-speed/non-volatile memory embedded in system LSIs.