San Jose (CA) - Rambus has demonstrated an XDR memory system capable of achieving data rates of up to 7.2Gbps. The system - showcased at the 2009 Denali MemCon - was comprised of Elpida's 1Gb XDR DRAM device, along with an XIO memory controller designed to transmit realistic data patterns. The XIO memory controller also demonstrated bi-modal operation with support for next-generation XDR2 DRAM.
According to Rambus, the XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, while the total memory system provides approximately twice the bandwith than GDDR5 at equivalent power.
"Future graphics and multi-core processors require significantly higher memory performance under extremely challenging power and thermal constraints," said Martin Scott, a senior Rambus VP. "This technology demonstration highlights the outstanding power efficiency of the XDR and XDR2 memory architectures at performance levels from 3.2 to 7.2Gbps with scalability to well over 10Gbps."
Scott explained that the demonstration incorporated technology developed as part of the company's Terabyte Bandwidth Initiative, including:
Scott also noted that an XDR2 memory system was capable of providing memory bandwidths of over 500GB/s to an SoC. For example, a single 4Byte-wide, 9.6Gbps XDR2 DRAM device delivers up to 38.4GB/s of peak bandwidth, while the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s.
The XDR memory architecture has already been adopted in a variety of products, including the Sony Playstation 3, DLP projectors, Teradici PC-over-IP computing systems, Toshiba's Qosmio laptop, as well as PCs and HDTV chip sets.