Intel develops integrated memory controller for Nehalem processors

  • Santa Clara (CA) – Just a few weeks ahead of its developer forum in Beijing, Intel has provided an update on the 45 nm Penryn processor family as well as the successor of the first generation Core architecture, which goes by the code-name “Nehalem.” The big news is the Intel will depart from the traditional front side bus and integrate the memory controller into the CPU.

    If that sounds like a familiar concept to you, then your instincts are right: AMD has been using an integrated memory controller for some time now in its Athlon 64/Opteron processors. And even for Intel this move has been more a matter of “when”, rather than “if”: Intel executives were routinely asked by journalists at briefings if an integrated memory controller (IMC) makes sense for Intel – a question which Intel routinely answered with the phrase the options are evaluated and that such a solutions would be introduced when it makes sense.

    Apparently, it makes sense to introduce an IMC with the Nehalem core, which will replace Core-based products starting in the second half of 2008. 45 nm Nehalem processors will arrive with up to eight cores and will include a “highly integrated” memory controller, referred to as “Nehalem system interconnect,” that aims to “deliver industry leading performance and capability for its targeted market segments,” Intel said. Basically, the technology (previously also known as Common System Interface or short “CSI”) represents a point-to-point serial bus, which removes a bandwidth bottleneck that has been building up in the front side bus over the past years.

    As reported by TG Daily in February, Nehalem will also bring back Hyperthreading that was originally introduced with the Pentium 4 series of processors and separated the processor in one physical and one virtual core. With Nehalem, Hyperthreading will be named “simultaneous multi-threading” and offer a maximum of 16 threads (with 8 physical cores). An interesting move is also the announcement that Nehalem processors will be available with integrated graphics, which is very reminiscent of AMD’s Fusion processor, which is believed to debut at the end of 2009 or early 2010. Intel calls Nehalem the first “truly dynamic and scalable microarchitecture” and said that it would provide more details further about it down the road.


    Before Nehalem hits the market, Intel will launch a refreshed a 45 nm shrink of the current Core 2 Duo processor generation, which is based on the 65 nm Merom core. The company once again built this new, refreshed processor around the mobile processor, code-named Penryn. There will also be a dual-core desktop-version “Wolfdale”, the quad-core “Yorkfield”, the dual-core “Wolfdale-DP” for Xeon volume servers, and the quad-core variant “Harpertown”. The first 45 nm processor will go into mass production in the second half of this year, with product announcements generally expected to be made either late in Q4 or early in Q1 2008.

    The Penryn family will come with L2 cache sizes of up to 6 MB in the dual-core segment and up to 12 MB in quad-core versions. Also new are the SSE4 instruction set as well as improved power management, which Intel calls “deep power down” and “enhanced dynamic acceleration.”

    Clock speeds of the new processors are largely under wraps, but it appears that the refreshed Core architecture will see rising frequencies again. Single-socket and dual-socket server processors will be available with more than 3 GHz, while maintaining a power envelope 40, 65 and 80 watts for the dual-core environment and 50, 80 and 120 watts for quad-core versions. 

    It didn’t take long for AMD to comment on Intel’s announcement. In a statement distributed to the press, corporate vice president Randy Allen said: "In mid-year, AMD will launch its native quad-core processor with an enhanced architecture, code-named "Barcelona." Our competitor's announcement today is further validation that their current architecture will not be competitive with Barcelona until they make this transition that we showed the industry in 2003 with Direct Connect Architecture.” Allen also pointed to the fact that AMD aims to provide its customers with a seamless upgrade to the quad-core processor generation: “We are not requiring our customers to make wholesale infrastructure changes in order to achieve incremental performance gains."

    What is your opinion? Is Intel’s introduction of an IMC too late? Will AMD lose its advantage? Use our discussion form below to let us and other readers know what you think.