Panasonic and Renesas said that the two companies will continue their joint development effort of production processes. The development of a 32 nm has begun and the firms are “confident” that that their 32-nm node transistor technology and other advances can “soon” be applied to products in mass production.

While Panasonic and Renesas said that it is always difficult to introduce new materials at a production process, the companies found that “the technology challenges in achieving acceptable transistor performance at the 32 nm node are more formidable than they were at previous-generation process nodes.”

The firms expect to clear the development hurdles with a 32 nm SoC process that uses a newly developed transistor technology with a metal/high-k gate stack structure and interconnect technology, that uses a new ultra-low-k material.

There is also a complementary metal-insulator semiconductor (CMIS) technology, a type of complementary Metal Oxide Semiconductor (CMOS) and an ultrathin film cap layer is applied at the atomic level to transistors with a metal/high-k gate stack structure. According to Renesas, this approach enables the development of a conventional transistor configuration, which allows the use of an oxidized silicon film as the gate insulation layer.

The Company claims that the cap layer will improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors – and enable large-scale circuits as a result.

There was no information hen 32 nm SoC will actually be available from Renesas and Panasonic. However, the firms noted that the SoCs will be targeted at “advanced mobile and digital home appliance products.”