SiCortex announced a newly added line of faster, more energy efficient MIPS-based systems used currently in high performance computing clusters.  These new processors literally double efficiency by increasing the clock speed and reducing power consumption in the same physical footprint (socket/system).  

SiCortex develops their high productivity computing (HPC) platforms from the silicon up.  The company designed a 6-core MIPS chip, called SiCortex SOC, each with its own 32 KB L1 instruction and data cache, built-in DMA and dual DDR2 memory controllers, undisclosed L2 cache size and 192 million transistors.  The chip communicates with traditional away devices through a high speed PCI-e path as well as an internal 6-lane fabric channel (3 in and 3 out) to coordinate off-node requests directly with other nodes nearby.

SiCortex's primary design goal was a high degree of scalability with a low degree of performance fall-off despite the many nodes.  Its systems can scale from 72 cores up to 5832 cores (972 nodes), all running Linux and other open-source code.  The maximum performance throughput is 5.8 TFlops with a maximum power consumption of less than 20 kWatts for an entire cabinet.

SiCortex SOCs are programmed with traditional C++ code, including open source STLs, libraries and modified specialty apps.  With this release, the firm’s optimizing compiler has also been enhanced to create smaller, faster, tighter code.