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Armonk (NY) - IBM announced yesterday a new toolset solution capable of creating chip features at the 22nm process node due out in 2011. Today's 45nm chips use a type of lithography which is not compatible with the 22 nm process node and that won't scale to such small levels. IBM's solution has turned away from strict optics into complex mathematics and promises to address the chip making needs of 2011 and beyond.
The new process is called Computation Scaling (CS) and is "a process that enables the production of complex, powerful and energy-efficient semiconductors at 22 nm and beyond." According to IBM's Semiconductor Research and Development Center VP, Gary Patton, "The traditional scaling approach is optical-resolution centric. IBM's CS approach is focused on advanced mathematical techniques encapsulated in software tools that use high performance computing systems. This technique also makes technology complexity transparent to the designer and maximizes flexibility through integrated flows and automation."
According to Patton, IBM has developed an entire production toolset which allows designers to do their magic creating the innards of CPUs, memory chips, DSPs and whatever else is required, and do so logically. Then, the tools convert and optimize everything specifically for this new manufacturing process that is not simply an optical shrink. This may be what IBM was referring to when they made their recent 22 nm SRAM announcement and promised a type of high-k metal gate technology that no one else is using. It may not have been strictly the materials involved that is unique, but also the entire process.
IBM's CS solution includes many stages or processes. These are "a new resolution enhancement technique, source mask optimization, virtual silicon processing with TCAD, predictive process modeling, design-rule generation and corresponding models, design tooling, design enablement, complex illustration, variance control and mask fabrication, along with necessary partnerships," the company said.