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| FSB limits exposed: Intel CPUs don’t scale very well in UC Berkeley HPC test |
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| Hardware | ||||
| By Theo Valich | ||||
| Tuesday, April 29, 2008 11:56 | ||||
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Berkeley (CA) – Researchers from the Computer Science Division at UC Berkeley and Lawrence Berkeley National Laboratories (CRD/NERSC) recently submitted a paper to the IEEE, highlighting the subject of scaling an optimized Lattice Boltzmann Simulation on popular supercomputer architectures. Intel may not be completely happy with the findings: At least in this very specific environment, the Xeon and Itanium 2 processors did not scale very well, while Sony’s Cell BE came out on top. The paper itself was published as “Lattice Boltzmann Simulation Optimization on Leading Multicore Platforms” and tries to shed some light on a specific area of socket-per-socket HPC (High-Performance-Computing) scaling in supercomputer environments. As reported first by HPC Wire, the scientists evaluated AMD’s Opteron (Santa Rosa), Intel’s Itanium 2 and Xeon (Clovertown), as well as the Sony-Toshiba-IBM Cell BE and Sun’s Niagara 2 processors. The researchers apparently spent quite some time on optimizing the application itself, rather than the hardware. This optimization was claimed to have resulted in a 14x improvement over the original LBMHD code (Lattice Boltzmann magneto-hydrodynamics). ![]()
According to the paper, the best scaling was delivered by the STI Cell BE system, followed by Sun’s Niagara 2, AMD’s Opteron, Intel’s Xeon and Itanium 2.
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Shop Keywords: Intel, FSB, memory, Nehalem, Cell BE, Haroertown, Opteron, Niagara 2