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| IDF Day 1: Penryn showcased, Nehalem revealed |
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| Wednesday, September 19, 2007 02:10 | ||||
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San Francisco (CA) – Day 1 of the Fall Intel Developer Forum 2007 has come to an end and we are digesting the news and information we have received so far. TG Daily's Rick Hodgin sums up his impressions about the key products at the show, Penryn and Nehalem.
![]() Paul Otellini with a wafer of 45 nm Penryn processors Otellini provided an overview of the history of the insulating layer which, in modern CPUs, is only five molecular layers of silicon dioxide (SiO2) thick. He explained that as far back as 15 years ago, Intel’s engineers saw this layer as problematic. The continued scaling of the insulating layer could not continue forever. And, we found out later in the day with Dr. Gordon Moore’s keynote, that five molecular layers is about the lowest you can go in practice. It’s a form of wall, and Intel was right up against it. Penryn will come with a hafnium-based hi-k dielectric and a metal gate solution. This technology helps to reduce gate leakage by 10x over existing models, according to Intel. This 10x reduction is not in an overall leakage reduction, but only gate leakage. We were told future solutions will address aspects of the remaining leakage, though no details or timeframes were disclosed. It’s interesting to note that Gordon Moore talked about hard limits being reached in 10-15 years. Up until now, he said, the walls which have been out there in front of the designers have always managed to fall down somehow. But now, they are real walls, ones which might truly stop further development until they are solved. Penryn also comes with some fairly significant architectural changes, which vary somewhat from what we have understood Intel’s tick-tock strategy to be. "Ticks" are described to be process revisions while "tocks" are supposed to be new processor architectures. Intel showed several slides indicating the same thing – but Penryn will be introducing fairly significant architectural changes that are much more than a refresh. These include Intel’s Wide Dynamic Execution engine with a new, untested Radix-16 divider (the first significant divider change in many years). Also, there are new components for faster OS responses and virtualization. There is the advanced smart cache of 12 MB, which is also 24-way set associative. Add to that Intel’s Smart Memory Access, new SSE4 instructions and a super-shuffle engine. And finally, there is a new deep power down mode (C6), which and allows logic units to off-load their state into other logic units for a truer power-down. Clock per clock, Penryns are faster, Intel said. It is unclear how much of this comes from the 50% larger L2 cache and how much comes from new architectures. Otellini, however, did indicate Penryns deliver 20% greater performance due to the 45nm hi-k/metal gate solution. Nehalem The big surprise of the day? Two live demonstrations of Nehalem in a physical machine. In the morning, we had a simple Nehalem system setup running Windows XP and a few applications. Otellini told us that Nehalems had been taped out for about a month, and what we saw was three week old "A0" silicon. He then held up a wafer showing wide, native quad-core Nehalems that were in use. Intel representatives made sure that they weren't using the AMD term “native quad-core” when describing Nehalem. Instead, they referred to it as "quad-core on a single die".
![]() 45 nm Nehalem CPUs on a wafer Another demonstration focused on the hyper-threading capability of Nehalems: Each core can support two threads. Intel showed off aa 16-thread machine, running two threads on eight cores in a dual-socket, quad-core configuration. The Nehalems were running 3D demos showing their I/O prowess with the GPUs. Nehalem will adopt nearly everything AMD has been touting with K8 and Barcelona. The architecture will see on-die memory controllers, "QuickPath" communication between sockets (formerly called "CSI" and comparable to HyperTransport), including a multi-ported crossbar for communicating in 4-way configurations. Nehalem will also come with a significantly larger L2 cache. It will be a full 12 MB, arranged in dual-banks of 6 MB per dual-core. While Nehalem is a single-die quad-core design, its cache is still broken out into two half-size segments. Nehalem is a behemoth at 820 million transistors, yet its die is only 107 mm2 in size. That’s 36 mm2 smaller than Penryn, which is expected to carry also 820 million transistors in its quad-core version (and 410 million in dual-core models.)
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Read all stories from TG Daily in our IDF Fall 2007 Wrap-up.
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