Tilera goes pro with TilePro64

  • San Jose (CA) - Tilera today announced the next generation of their tile-based processors. A follow-on to their previous Tile64 embedded CPUs, two new TilePro models offer 36 and 64 cores with notably greater performance per watt. A toolset revision called Multicore Development Environment (MDE) 2.0 allows full emulation and simulation with clock cycle granularity.

    Tile64 to TilePro36 and TilePro64

    Tilera uses a common multi-core approach to design both for their older Tile64 and the new TilePro lines. A single core is created, perfected, validated and tested. Once it's working it is replicated as many times as are needed for the silicon die.

    The original Tile64 offered only a 64-core version. This new release introduces a 36-core version called TilePro36 (in addition to the 64-core version). TilePro36 uses a scaled down implementation of their 64-core product designed to increase yields and provide a lower-power mid-range product. Tilera is continuing to expand its design and products with more than 64 cores are planned, TG Daily was told.

    Same process technology

    Tile64 and TilePro are both manufactured using a 90 nm process generation. Tilera claims an increase in performance of 1.5x to 2.5x in TilePro. Fed primarily by a doubling of the L1 cache size per tile and doubling of the L2 associativity, the addition of a new communication channel and benefits given by added instructions through recompilation, all for an increase of 5% in overall power consumption. Unit pricing will increase from $435 per chip in 10K unit quantities for Tile64, to around $900 per chip for TilePro64 in 200 unit quantities.  Development boards and MDE 2.0 software cost $18,000.

    New instructions

    Tilera introduced several new instructions with TilePro, including some for multimedia, unaligned loads, memory and fence hints as well as offset load/store instructions. The company claims the new multimedia instructions double the throughput and performance of audio codecs, as well as echo cancellation processing. The new offset load/store instructions increase video encoding by 50% and the unaligned loads are now 60% faster.

    Fully compatible

    TilePro is both binary and socket compatible with Tile64. Existing customers can literally pop out their old chips, pop in the new ones and be up and running without any changes to software. Customers will see an immediate increase in performance due to the larger cache, according to teh company. However, there are features added to the new cores which require a recompilation (such as the new instructions and additional communications lane).

    Tilera Comparison Chart
    DescriptionTilera Tile64Tilera TilePro36Tilera TilePro64
    IntroducedJul 17, 2007Sep 22, 2008Sep 22, 2008
    Core Clock500,700,866 MHz500 MHz700,866 MHz
    DDR2 Clock667,800 MHz533 MHz800 MHz
    DDR2 controllers434
    DDR2 efficiency55%70%+70%+
    PCI-e controllers212
    10 GbE + XAUI212
    Misc I/O10 Gbps10 Gbps10 Gbps
    Flexible I/O20 Gbps20 Gbps20 Gbps
    Max realtime I/O50 Gbps30 Gbps50 Gbps
    Max intra-die I/O31 Tbps20.9 Tbps37.2 Tbps
    Mesh traffic32 bits/clock
    full duplex
    32 bits/clock
    full duplex
    32 bits/clock
    full duplex
    "Direct-to-tile" I/O?NoYesYes
    max Watts221623
    L1 Cache/core8KB Instruction
    8KB Data
    16KB Instruction
    8KB Data
    16KB Instruction
    8KB Data
    L2 Cache/core64KB64KB64KB
    Cache line64 bytes64 bytes64 bytes
    Possible L3 Cache4MB2.3MB4MB
    Dedicated coherency network?NoYesYes
    16-bit flops221 Gflops144 Gflops221 Gflops
    32-bit flops166 Gflops54 Gflops166 Gflops
    16-bit Flops/watt10.057.139.61
    32-bit Flops/watt7.553.387.22
    16-bit Flops/core3.453.173.45
    32-bit Flops/core2.591.52.59
    Dual endian support?NoYesYes
    Memory striping?NoYesYes
    Cache distributable to other tiles?YesYesYes
    ISA64-bit VLIW
    64-bit VLIW
    64-bit VLIW
    Socket1517 BGA1517 BGA1517 BGA
    Package40mm x 40mm40mm x 40mm40mm x 40mm

    Tilera is still in startup company mode, funded by venture capitalists. Its first commercial product was announced in August, 2007, though they have said samples were shipped as early as June, 2007.  That announcement took the company out of "stealth mode" even though volume products were not available until April, 2008. Tilera now claims to have more than 45 customers, many of which were taken directly from high-speed technology fields, such as those typically employing custom ASICs and FPGAs.

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